Overcoming wiring delay, clock power consumption
As process technology has progressed from 65 nm to 28 nm and beyond, the delay of wiring has come to dominate logic delay, due to poor scaling of metal wire and via resistance. To some extent, this can be mitigated by widening the wires, but that adds to the die area and cost. So, with each succeeding generation of process technology, inter-cluster delay becomes a significant contributor to the critical path, thus diminishing the speed advantage of six-input LUTs.
An example of the advantages of such a fabric design is Microsemi’s PolarFire FPGA family, which provides rapid direct connections between nearby LUTs. This can reduce intra-cluster delay, especially in conjunction with advanced synthesis and placement algorithms.
Certain logic functions (such as MUX trees) greatly benefit from the direct connections.
Another focus of today’s latest FPGA fabrics is clock dynamic power. Clocks can be a significant contributor to dynamic power in mid-range system applications, often consuming nearly as much power as the rest of the routing and logic. For this reason, clocks should be designed to conserve power. This means allocating more area to clock wires to space them further apart, significantly reducing their capacitance and dynamic power.